Phase change non-volatile memories, so-called embedded Phase change Memories (ePCMs), represent a new generation of integrated memories. In these memories, in order to store information, the characteristic of materials having the property of switching between phases with different electrical characteristics is relied upon. These materials may switch between an amorphous, disorderly, phase and a crystalline or polycrystalline, orderly, phase, and the two phases are associated to resistivities of considerably different value, and consequently to a different value of a stored data. For example, the elements of the VI group of the periodic table, such as tellurium (Te), selenium (Se), or antimony (Sb), referred to as chalcogenides or chalcogenic materials, may be advantageously used for manufacturing phase change memory cells. In particular, an alloy made up of germanium (Ge), antimony (Sb), and tellurium (Te), known as GST (having the chemical composition Ge2Sb2Te5), is currently widely used in such memory cells.
The phase changes can be obtained by locally increasing the temperature of the cells made of chalcogenic material, and through resistive electrodes (generally known as heaters) in contact with respective regions of chalcogenic material. Selection devices (for example, MOSFETs) are connected to the heaters and enable passage of a programming electric current through a respective heater. This electric current, by the Joule effect, generates the temperatures necessary for the phase change. In particular, when the chalcogenic material is in the amorphous state, at high resistivity (the so-called RESET state), it may be required to apply a current/voltage pulse (or an appropriate number of current/voltage pulses) of duration and amplitude such as to enable the chalcogenic material to cool slowly. Subjected to this treatment, the chalcogenic material changes its state and switches from the high-resistivity state to a low-resistivity state (the so-called SET state). Vice versa, when the chalcogenic material is in the SET state, it may be required to apply a current/voltage pulse having appropriate duration and high amplitude so as to cause the chalcogenic material to return to the high-resistivity amorphous state.
During reading, the state of the chalcogenic material is detected by applying a voltage sufficiently low as not to cause a sensible heating thereof, and then by reading the value of the current in the memory cell. Given that the current is proportional to the conductivity of the chalcogenic material, it is possible to determine in which state the material is, and consequently determine the data stored in the memory cell. In general, PCMs provide important advantages, amongst which are high scalability and reading speed combined with a reduced current consumption and a high efficiency.
As shown in FIG. 1 (limited in detail, as will be appreciated by those skilled in the art), a non-volatile PCM device 1 comprises a memory array 2 made up of a plurality of memory cells 3, arranged in rows (word lines, WL) and columns (bit lines, BL). Each memory cell 3 comprises a storage element 3a and a selector element 3b, which are connected in series between a respective bit line BL and a terminal at a reference potential (for example, ground, GND). In particular, a word line WL is defined by the set of all the control terminals of the selector elements 3b aligned along one and the same row.
The storage element 3a includes a phase change material (for example, a chalcogenide, such as GST), and is consequently able to store data in the form of resistance levels associated to the different phases assumed by the material. The selector element 3b, as in the embodiment illustrated, may be an NMOS transistor having its gate terminal connected to the word line WL, its drain terminal connected to the storage element 3a, and its source terminal connected to the terminal at reference potential. The selector element 3b is controlled so as to enable, when selected, the passage of a reading/programming driving current through the storage element 3a, during respective reading/programming operations.
A column decoder 4 and a row decoder 5 enable selection, on the basis of address signals received at input and complex decoding schemes of the memory cells 3, of the corresponding word lines WL and bit lines BL. Each time the memory cells are addressed, the biasing thereof is enabled at appropriate voltage and current values by corresponding driving stages. In particular, as shown in FIG. 1, the driving stage 6 supplies the driving currents for the bit lines BL of the memory array 2 during the operations of programming of the SET or RESET states in the memory cells 3.
In particular, it is known that the programming operations, both when programming of the SET state and when programming of the RESET state, of the chalcogenide material of the memory cells 3 envision a supply to the storage elements 3a of current pulses of high value, for the activation of the mechanisms of change of state. Moreover, an accurate control of the parameters of the programming current pulses is critical for ensuring efficient and repeatable transitions between the SET and RESET states, and this control must be ensured in a wide range of values of current so as to deal with the various operating conditions of the memory device 1. For example, a low distortion of the waveform of the driving current pulses may be required in a wide range between 100 μA and 1000 μA (with a maximum voltage generated on the bit lines BL by the column decoder 4 that may reach a value of approximately 3 V, and a voltage on the word lines WL of a value around 2.7 V).
The programmed SET state may undergo shifts of several microamps in the case where the SET current pulse deviates significantly from the optimal, desired, one, and that in general, this deviation should not exceed +/−10% (for example: 200 μA+/−20 μA), taking into account both systematic errors and statistical errors. By way of example, FIGS. 2a and 2b show possible plots of the RESET pulses and of the SET pulses, respectively, for the respective operations of programming of the memory cells 3. It is evident that meeting of the aforesaid stringent requirements in the control of the parameters of the waveforms of the programming current pulses is an aspect that may be addressed in the design of memory devices and that may represent one of the aspects thereof.
FIG. 3 is a driving stage 6 for supplying, during programming operations, output driving currents, here designated by Ik (where k is an index of integer value, for example, ranging between 0 and 31, in the case where the driving stage 6 is connected to thirty-two bit lines BL) designed for biasing the memory cells 3. The output driving currents Ik are supplied to the column decoder 4, so as to subsequently be supplied, according to the decoding schemes implemented, to the bit lines BL of the memory array 2.
In detail, the driving stage 6 comprises a driving-control unit 7 having a low-impedance input receiving an input current Iin of a low value (i.e., sensibly lower than the value required for the output driving currents Ik), for example, equal to 200 μA in the case where the value required for the output driving current Ik is 800 μA, generated by an input stage 8 as a function of the specific required memory operation (for example, having a different value for the SET and RESET programming operations). This input-current-generator stage 8 may be implemented in a wide range of ways, generally depending on the type of application. For example, a digital-to-analog converter (DAC) may be used, whereby a given output current corresponds to a given configuration of a certain number of input bits.
The driving stage 6 further comprises an output driving unit 9 connected to the driving-control unit 7 and designed to generate and distribute to the bit lines the output driving currents Ik. The driving-control unit 7 and the output driving unit 9 are supplied by a charge-pump stage 10, which supplies appropriate supply electrical quantities, in particular, a boosted voltage Vcp in the high-voltage (HV) range (for example, between 4 V and 5 V) of a value higher than the low logic voltages used in the memory device 1 (which are, for example, between 1.08 V and 1.32 V).
The driving-control unit 7 comprises a plurality of control subunits 11, and the output driving unit 9 comprises a respective plurality of driving subunits 12, each of which, appropriately supplied by the charge-pump stage 10, is designed to supply a respective output driving current 1k, having a value amplified by a factor β with respect to the input current Iin, according to the relation: Ik=Iin·β. The voltages supplied at output by the driving subunits 12 are, for example, approximately 3 V.
In particular, each control subunit 11 drives in an appropriate way a respective set of driving subunits 12, supplying appropriate command signals for enabling supply at output of the respective output driving currents Ik. For example, each control subunit 11 can drive four respective driving subunits 12 (so that in the driving stage eight control subunits 11 may, for example, be present, for supplying thirty-two output driving currents Ik via a corresponding number of driving subunits 12).
As illustrated in FIG. 4 (which depicts, for simplicity of illustration, a single control subunit 11 and the corresponding set of driving subunits 12, illustratively four in number), each control subunit 11 forms, with the corresponding set of driving subunits 12, a current mirror in cascode configuration, designed to mirror on the various outputs the input current Iin with amplification factor R. The control subunit 11 defines the input branch of the current mirror while the driving subunits 12 define respective output branches of the same mirror, connected to one another in parallel.
In more detail, the control subunit 11 comprises a cascode control transistor MCC and an input mirror transistor MPC, both of a PMOS type and connected in series between a first input In1 of the driving stage 6. The driving stage receives the input current Iin, and a second input In2 of the same driving stage is connected to the output of the charge-pump stage 10 and receives the boosted voltage Vcp. The control terminal of the cascode control transistor MCC is connected to a third input 1n3, which receives a cascode biasing voltage Vcascp, of an appropriate value, while the control terminal of the input mirror transistor MPC is connected to the first input In1 and to the respective conduction terminal of the cascode control transistor MCC, so as to provide the diode configuration for the current-mirroring operation.
Each driving subunit 12 (for convenience, an n-th driving subunit 12 is described, but altogether similar considerations apply to the other subunits of the corresponding set, designated by n+1, n+2 and n+3, where n is an integer index representing the set itself) comprises a respective cascode driving transistor MCn and an output mirror transistor MPn, both of a PMOS type and connected in series between the second input In2 and a respective output of the driving stage 6 that supplies the respective output driving current In. The control terminals of the cascode driving transistor MCn and of the output mirror transistor MPn are connected to the control terminals of the cascode control transistor MCC and of the input mirror transistor MPC, respectively.
The circuit configuration described may enable mirroring of the input driving current Iin with the desired amplification factor β, given by the different size ratios (width/length, W/L) of the transistors in the input and output branches. In particular, the cascode configuration may enable a drain-to-source voltage drop Vds to be obtained at the output mirror transistors MPn that is substantially constant, so as to ensure repeatability of the electrical performance. The cascode configuration may enable linearity to be obtained both for the driving-control unit 7 and for the output driving unit 9.
However, the configuration described also may have some limitations that do not enable full exploitation of its advantages. In particular, for reasons of speed and consumption, each control subunit 11 may drive a limited number (for example, three or at the most, as in the case illustrated, four) of driving subunits 12 connected in parallel so that a considerable occupation of area is required for the integrated implementation of the single driving-control unit 7. Moreover, it may be required that all the transistors in the circuit are of the high-voltage type in order to withstand the high voltage values present across their terminals, which, combined with the high requirements of output current, entails the use of transistors of large dimensions, with thick oxides, and high costs, and once again a considerable occupation of space. Given that the entire driving stage 6 is supplied by the charge-pump stage 10, the latter must be sized so as to meet the high current requirements thereof, and in particular the inefficiency of the driving stage 6 itself results in a high consumption of current required of the charge-pump stage 10.
Moreover, the circuit described, in cascode configuration, operates effectively and shows a good linearity when the driving-control unit 7 operates in the high-voltage range in such a way as to ensure a sufficient drain-to-source voltage drop Vds on the output mirror transistors MPn. Instead, it is evident that the cascode configuration has some limitations in the case where the driving-control unit 7 is supplied with low voltages (for example, around the value of a logic supply voltage Vdd of the memory device 1).